Mentor Graphics: Digital – Scalable Verification

Questa AFV (Advanced Functional Verification)
The first standards-based, single-kernel verification platform that integrates an HDL simulator, a constraint solver, an assertion engine, functional coverage and a common user interface. The platform also offers built-in support for testbench automation (TBA). coverage-driven verification (CDV), assertion-based verification (AVB), and transaction-level modeling (TML).

Questa SV (SystemVerilog)
The first SystemVerilog, single-kernel verification environment wth a constraint solver, an assertion engine, functional coverage and a common user interface. Questa SV also provides a complete SystemVerilog design environment and built-in support for testbench automation (TBA), coverage-driven verification (CDV), and assertion-based verification (ABV).

0-In® Assertion Synthesis
0-In Assertion Synthesis allows customers to reach verification closure more efficiently and more effectively. Assertion Synthesis is the result of combining the industry's most powerful and easy-to-use verification IP with technologically superior tools and clear methodologies honed on real customer designs. The result is a complete assertion solution that delivers significant risk reduction and rapid return on investment for customers.

0-In Formal Verification
The 0-In Formal Verification solution is easy to use and provides value throughout the design cycle - from block-level design, where it replaces traditional block-level simulation test benches, to chip-level design, where it replaces extensive pseudo-random simulation. 0-In Formal Verification integrates the industry's most powerful static and dynamic formal verification technologies with the industry's most comprehensive assertion-based verification (ABV) solution, enabling users to achieve functional verification closure quickly and predictably.

0-In® Clock-Domain Crossing (CDC)
0-In CDC is the industry's most comprehensive and easy-to-use Clock-Domain Crossing verification solution, integrating advanced verification engines with engineered methodologies. Using 0-In CDC, customers can efficiently and effectively eliminate all clock-domain crossing problems from their designs.

ModelSim® SE
Tri-lingual simulator with VHDL, Verilog, and SystemC, combining high performance with the most advanced debugging capabilities in the industry.

ModelSim® LE
Linux-based simulator with Dataflow Window and Waveform Compare for better debug productivity.

ModelSim® PE
The industry-leading, Windows-based simulator for VHDL, Verilog, or mixed-language simulation environments.

Advance MS
ADVance MS is a language-neutral, mixed-signal simulator that enables top-down design and bottom-up verification of multi-million gate analog/mixed-signal system-on-chip designs.

ADVance MS RF
Industry-leading tool for mixed-signal simulation

Seamless
Co-verification environment that detects and isolates hardware/software interface errors.

Seamless FPGA
Co-verification environment that detects and isolates hardware/software interface errors for Platform FPGAs and systems for these devices.


** For more info, please visit www.mentor.com

Back