Mentor Graphics: IC Nanometer Design

Design Architect-IC
Design Architect-IC is a powerful tool for schematic capture, netlisting, simulation setup and results viewing, all integrated within the Mentor Graphics analog/mixed-signal SoC design flow. Design Architect-IC integrates seamlessly with the Mentor Graphics IC Station SDL application to conceptualize, develop, simulate and verify the most challenging designs quickly and accurately--the first time.

ADVance MS (ADMS)
ADVance MS is the industry's first mixed-signal simulator that brings together digital and mixed-signal standard HDL's with SPICE in a single environment.

Eldo RF
Eldo RF extends the Eldo transistor-level simulator into the realm of RF IC design. Through the use of 3rd-generation, multi-tone algorithms, Eldo RF is capable of simulating RF ICs with thousands of devices at levels of performance not available before. Eldo™
Uncompromised accuracy and far superior performance are the key benefits of the Eldo simulator. For SPICE-level analysis of the most complex circuits, Eldo provides both classical (Newton-Raphson) and advanced (OSR and IEM) algorithms. A unique partitioning scheme allows use of different algorithms on different portions of a design.

Mach TA
Mach TA™ is an accelerated simulation engine that accurately verifies transistor-level timing of the largest digital IC designs up to 1,000 times faster than SPICE-based circuit simulators. IC Station SDL
The Mentor Graphics IC Station SDL bundle includes all of the functionality ICgraph Basic, and adds a hierarchical, schematic-driven layout environment to create IC layouts based on information from a logic source, plus ready-to-use parameterized device generators for digital and analog layout design.

ICgraph Basic
ICgraph Basic offers an extensive set of functions for efficient, accurate polygon editing. This gives the layout engineer full control of circuit density and performance, while improving productivity to help meet time-to-market objectives.

ICassemble
As the digital content in today's mixed-signal SoC designs continues to grow, floor planning and routing is becoming increasingly important component of the design flow. To address the complexities of analog/mixed-signal chip assembly, Mentor Graphics developed ICassemble, which provides a robust set of features for floor planning, top-level assembly and interactive routing.

AutoCells
A standard cell place & route tool for the digital portion of Mentor Graphics' IC flow.

HotPlot Bundle
The HotPlot stand-alone high-speed printing environment eliminates bottlenecks in your design process by getting the most complex designs out to the plotter faster than any other plot solution available on the market today.

Calibre DRC
The industry standard for design rule checking. Offers virtually unlimited capacity for all physical designs. Offers easy-to-use automatic analysis and optimization of hierarchy for execution efficiency across all design styles. Provides the fastest methods possible to identify and repair LVS issues, including complex power-to-ground short circuits. Seamless interface within many design environments

Calibre LVS
Industry standard physical verification tool for layout versus schematic. Delivers results in hours vs. days for both flat and hierarchical algorithms. Allows virtually unlimited capacity for hierarchical designs. Offers easy-to-use automatic analysis and optimization of hierarchy for execution efficiency across all design styles. Seamless interface within many design environments.

Calibre DESIGNrev
For engineers integrating and assembling complete chips, the process of going from first pass integration to successful tape-out can be lengthy and difficult. With design size and complexity increasing, traditional layout editors lack the capability to quickly and efficiently visualize, revise and stream-out layout data. Performing simple tasks on full-chip GDSII files, such as opening, viewing, revising or streaming-out, often can take hours. This nnecessarily delays tape-out schedules.

Calibre Interactive
Mentor Graphics' Calibre Interactive™ complements the Calibre full-chip physical verification tool by enabling designers to perform interactive verification of cells and blocks from within their familiar IC layout environment, including Cadence Design Systems' Virtuoso™ and Mentor Graphics' own IC Station.®

Calibre RVE
Quick, Intuitive Debugging in Cell/Block and Full-Chip Designs. Allows cross probing of results between layout, schematic, source netlist, layout netlist and LVS result files. Enables viewing of all parasitics in the Parasitic Browsing window. Highlights to schematic capture tools. Automated short isolation debugging. Fast and intuitive hierarchical SPICE browser for source and layout netlists.

Calibre xRC Parasitic Extraction
Calibre xRC is fully integrated with the Calibre product family as well as within popular layout environments. A tight link to Calibre LVS enables back annotation to the source schematic. Parasitic information is stored in the parasitic database for on-call mixed-level analysis.

Calibre xL
Full-chip, high-performance parasitic inductance extraction for analog, RF and custom digital nanometer designs. Full-chip, high-performance, parasitic self- inductance extraction. Accurate extraction of frequency dependent loop inductance and resistance. Efficient, realizable model order (RLC) reduction. Return-path selection and net-based extraction frequency selection. Fully integrated with Calibre LVS and xRC.

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